What are the fifo memory chip models?

Fifo memory

FIFO (First Input First Output) simply means FIFO. Due to the rapid development of microelectronics technology, the capacity of new generation FIFO chips is getting larger and smaller, and the volume is getting smaller and smaller, and the price is getting cheaper and cheaper. As a new type of large-scale integrated circuit, FIFO chips are increasingly used in high-speed data acquisition, high-speed data processing, high-speed data transmission, and multi-machine processing systems due to their flexible, convenient, and high-efficiency characteristics.

In system design, FIFO memory is widely used for the purpose of increasing data transmission rate, processing a large number of data streams, and matching systems having different transmission rates, thereby improving system performance. The FIFO memory is a first-in, first-out, dual-port buffer in which the first data entered therein is first shifted out, with one memory input port and the other memory output port. For a single-chip FIFO, there are two main structures: trigger-oriented structure and zero-oriented transmission structure. The FIFO of the trigger-oriented transfer structure is composed of a register array, and the FIFO of the zero-oriented transfer structure is composed of a dual-port RAM having read and write address pointers.

Features

The FIFO memory is the buffering part of the system. If there is no FIFO memory, the whole system cannot work normally. It mainly has several functions:

1) Cache continuous data streams to prevent data loss during incoming and storage operations;

2) The data is gathered together into the machine and stored to avoid frequent bus operations and reduce the burden on the CPU.

3) Allow the system to perform DMA operations to increase data transfer speed. This is a crucial point. If you do not use DMA operation, data transmission will not meet the transmission requirements, and it will greatly increase the burden on the CPU and cannot complete the data storage at the same time.

Therefore, choosing the right memory chip is very important for improving the system performance. In past designs, the â€œPing-Pongâ€ storage method is often used. This method uses two pieces of memory, and the data first enters one of them. When the data is full, Let the data enter the second piece of memory, and at the same time, the data in the first piece of memory is removed through logic control, and so on. Two pieces of data are buffered in turn. This method has obvious disadvantages. Firstly, the control is complicated and special logic is needed to maintain this rotation mechanism. Secondly, the flow of data flow must be constantly changed, which limits the data flow rate and is also prone to interference. From the data transmission point of view, the greater the capacity of the cache chip, the lower the requirement for subsequent timing, which can reduce the frequency of bus operations; but from the perspective of data storage, it means that there is a need to open up more memory space for buffering. Increase the computer's memory overhead, and the larger the capacity, the higher the cost. Therefore, based on a comprehensive consideration of system performance and cost, a chip that satisfies the system needs can be selected.

FIFO is the abbreviation of First In/First-Out. It means first in, first out. The FIFO memory is divided into a write private area and a read private area. The read operation and the write operation can be performed asynchronously, and the data written on the write area is read from the area of â€‹â€‹the read terminal in the order of writing, similarly to a kind of buffer absorbing the speed difference between the write end and the read end. The computer's serial port, in general, also has a FIFO buffer (not a single FIFO memory, but embedded inside the device).