WP_491 turns floating point to fixed point, greatly reducing power consumption and cost

Turn floating point to fixed point, significantly reducing power consumption and cost

(WP491)

Xilinx devices and tools support a wide range of data types, from binary to double precision. The scalable accuracy of the UltraScale architecture provides great flexibility to optimize power and resource utilization while meeting design performance goals.

Summary

In data center, aerospace and military, 5G wireless, and automotive, customers must meet the stringent thermal, power, and cost requirements of advanced driver assistance (ADAS), radar, and deep learning applications.

An extremely effective way to achieve these goals is to implement a signal processing chain with fixed-point numbers. Xilinx FPGAs and SoCs have inherent variable accuracy support that allows customers to easily adapt to this evolving industry trend toward lower precision solutions.

Xilinx offers a tool flow that includes Vivado® High Level Synthesis (HLS), allowing customers to easily evaluate lower precision implementations of C/C++ designs, such as fixed points.

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Positive article section

● Introduction: Data types supported by Xilinx

Xilinx All Programmable devices and tools support a wide range of data types, from binary to double precision floating point. Designs implemented with fixed points are always more efficient than the same design implemented with floating point because the fixed point implementation consumes less resources and consumes less power. If you move your design to a fixed point, it's not uncommon to cut power and footprint by half.

● The advantage of floating point conversion to fixed point

For almost all current designs, minimizing power consumption is a priority. Most applications must meet stringent power and cooling requirements before they can be put into production. A generally accepted principle is that floating point designs consume more power than low precision designs.

● Example: Convert floating point FIR filter to fixed point

The simple FIR filter design in Vivado HLS can be used to demonstrate how a floating-point FIR design can be converted to a fixed-point design to reduce the resources and power used and achieve similar results accuracy.

● greatly reduce the occupation of FPGA resources

The fixed-point FIR in this example occupies less than one-fifth of the original floating-point FIR.

● achieve significant power savings

Comparing the power estimation results of the two implementations of the single FIR filter in this white paper, the power consumption of the fixed-point FIR is reduced by 1.4W.

● Reduce material costs

Converting floating-point designs to fixed-point solutions can greatly reduce FPGA resource footprint. The reduction in FPGA resources can reduce material costs. It is implemented in three ways.

● Similar accuracy

By comparing the outputs of the two implementations of a single FIR filter design, it is found that the fixed-point implementation provides similar filter accuracy with a loss of accuracy of only -100dBm to -160dBm while reducing power consumption and cost.

● Reduce the delay

For a single FIR design example, the delay can be reduced by the filter—the fixed-point implementation is 12 clock cycles and the floating-point design is 91 clock cycles. As resource usage decreases, especially with the DSP48E2 Slice, it is expected to reduce latency.

Click " Read the original " to download the full Chinese version of WP491